Debouncer

--- Alexander Hoffman
--- 42004259

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clkdiv is
    Port ( mclk : in  STD_LOGIC;
           clr : in  STD_LOGIC;
 inp : in  STD_LOGIC;
           outp : out  STD_LOGIC);
end clkdiv;

architecture Behavioral of clkdiv is

signal q : STD_LOGIC_VECTOR(19 downto 0);
signal delay1,delay2,delay3: STD_LOGIC;

begin
process(mclk,clr)
begin
if mclk'event and mclk = '1' then

if clr ='1' then
q <= X"00000";
delay1 <= '0';
delay2 <= '0';
delay3 <= '0';
elsif q < X"403f6" then
q <= q + 1;
else
q <= X"00000";
delay1 <= inp;
delay2 <= delay1;
delay3 <= delay2;
end if;

end if;
end process;


outp <= delay1 and delay2 and delay3;

end Behavioral;