0.5Hz Clock, Csse Homework

--- Alexander Hoffman
--- 42004259

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clkdiv is
    Port ( mclk : in  STD_LOGIC;
           clr : in  STD_LOGIC;
           clk05 : out STD_LOGIC);
end clkdiv;

architecture Behavioral of clkdiv is

signal q : STD_LOGIC_VECTOR(27 downto 0);
signal r : STD_LOGIC;

begin
process(mclk,clr)
begin
if mclk'event and mclk = '1' then
if clr ='1' then
q <= X"0000000";
r <= '0';
clk05 <= r;
elsif q < X"2faf080" then
q <= q + 1;
else
q <= X"0000000";
r <= not r;
clk05 <= r;
end if;
end if;
end process;

end Behavioral;