Csse week 7 class lock

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity New_FSM is
    Port ( clk : in  STD_LOGIC;
           input : in  STD_LOGIC_VECTOR(2 downto 0);
     lock : in STD_LOGIC;
           right : out  STD_LOGIC;
     wrong : out STD_LOGIC);
end New_FSM;

architecture Behavioral of New_FSM is
 TYPE StateType IS
  (S_Initial,S_1right,S_2right,S_3right,S_1wrong,S_2wrong,S_3wrong);
 signal currentstate, nextstate: StateType;
begin
-- TODO: The next step is to define the actual transitions.
-- The Transitions are what happens on the actual clock edge.
-- Because the machine that we are building is relatively simple, the value of the Next State
-- will always go to the Current state on the rising edge of a clock.
-- i.e. Current state is assigned the value of Next state on the rising_edge of the clock input.
 process(clk)
 if(rising_edge(clk)) Then
  currentstate <= nextstate;
 end if;
end process;

process(currentstate, lock, load)
begin
 case currentstate is
   when S_Initial =>
    right='0';
    wrong = '0';
    if load = '1' then
     if input = "011" then
      nextstate <= S_1right;
     else
      nextstate <= S_1wrong;
     end if;
    end if;
   when S_1right =>
    right='0';
    wrong = '0';
    if load = '1' then
     if input = "001" then
      nextstate <= S_2right;
     else
      nextstate <= S_2wrong;
     end if;
    end if;
   when S_2right =>
    right='0';
    wrong = '0';
    if load = '1' then
     if input = "100" then
      nextstate <= S_3right;
     else
      nextstate <= S_3wrong;
     end if;
    end if;
   when S_3right =>
    right = '1';
    wrong = '0';
    if lock ='1' then
     nextstate <= S_inital;
    end if;
   when S_1wrong =>
    right = '0';
    wrong = '0';
    if load = '1' then
     nextstate <= S_2wrong;
    end if;
   when S_2wrong =>
    right = '0';
    wrong = '0';
    if load = '1' then
     nextstate <= S_3wrong;
    end if;
   when S_3wrong =>
    right = '0';
    wrong = '1';
    if load = '1' then
     if input = "011" then
      nextstate <= S_1right;
     else
      nextstate <= S_1wrong;
     end if;
    end if;
   when others => nextstate <= S_initial;
 end case;
end process;

end Behavioral;