CSSE hardware quiz 1 VHDL code

#################### NOTAND.VHD###############################

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity notand is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           f : out  STD_LOGIC);
end notand;

architecture Behavioral of notand is

begin

process(a,b)
begin
f<= a nand b;
end process;

end Behavioral;

###############################################################

##########################################QUIZ.VHD############

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity quiz is

    Port ( a : in  STD_LOGIC;

           b : in  STD_LOGIC;

           f : out  STD_LOGIC);

end quiz;

architecture Behavioral of quiz is

component notand is

port( a : in std_logic;

b : in std_logic;

f : out std_logic);

end component;

signal s1,s2,s3 : std_logic;

begin

c1: notand port map (a,b,s1);

c2: notand port map (s1,a,s2);

c3: notand port map (s1,b,s3);

c4: notand port map (s2,s3,f);

end Behavioral;

###############################################################

###########################CONSTRAINTS.UCF###################

net "a" loc = "p38";

net "b" loc = "p36";

net "f" loc = "p15";

##############################################################