Final power shizzle

MAX756

http://au.element14.com/maxim-integrated-products/max756cpa/step-up-reg-3v-5v-out-dip8-756/dp/1290853
http://www.farnell.com/datasheets/60116.pdf

Schottky Diode

http://au.element14.com/hy-electronics/1n5817/schottky-diode-1a-20v-do-41/dp/1843507

Capacitors

150uF
100uF
0.1uF

Inductors

22uH

3V to 5V Charge Pump IC 125mA output current

2 Options

Cheap option.

MAX1595 http://www.farnell.com/datasheets/86683.pdf

http://au.element14.com/maxim-integrated-products/max1595eua50/ic-charge-pump-reg-5-0v-8-umax/dp/1673185

@ 3V in,  I over load is 125mA dropping to 75mA at  2V input.

Circuitry more complex and probably more expensive with diodes required.

More expesive IC but overall possibly cheaper

MAX757 http://www.farnell.com/datasheets/60116.pdf

http://au.element14.com/maxim-integrated-products/max757csa/ic-dc-dc-conv-3-3v-5v-8-so/dp/1673219

@ 3v in, I over load is 200mA

POWAH

http://au.element14.com/taiwan-semiconductor/1n5818/diode-rectifier-30v-1a-do41/dp/1864598
http://www.farnell.com/datasheets/42755.pdf

Power Supply Circuit

http://www.farnell.com/datasheets/42755.pdf

1.5V to 5V Boost Switch Mode Power Supply

http://www.daycounter.com/Calculators/Switching-Converter-Calculator.phtml

http://services.eng.uts.edu.au/~venkat/pe_html/ch07s3/ch07s3p1.htm

Diode Rectifier Simulations

50Hz

200Hz

500Hz

1000Hz

2000Hz

4000Hz

8000Hz

16000Hz

hahaha

baz loves hoff not cookie

Debouncer

--- Alexander Hoffman
--- 42004259

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clkdiv is
    Port ( mclk : in  STD_LOGIC;
           clr : in  STD_LOGIC;
 inp : in  STD_LOGIC;
           outp : out  STD_LOGIC);
end clkdiv;

architecture Behavioral of clkdiv is

signal q : STD_LOGIC_VECTOR(19 downto 0);
signal delay1,delay2,delay3: STD_LOGIC;

begin
process(mclk,clr)
begin
if mclk'event and mclk = '1' then

if clr ='1' then
q <= X"00000";
delay1 <= '0';
delay2 <= '0';
delay3 <= '0';
elsif q < X"403f6" then
q <= q + 1;
else
q <= X"00000";
delay1 <= inp;
delay2 <= delay1;
delay3 <= delay2;
end if;

end if;
end process;


outp <= delay1 and delay2 and delay3;

end Behavioral;

Csse week 7 class lock

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity New_FSM is
    Port ( clk : in  STD_LOGIC;
           input : in  STD_LOGIC_VECTOR(2 downto 0);
     lock : in STD_LOGIC;
           right : out  STD_LOGIC;
     wrong : out STD_LOGIC);
end New_FSM;

architecture Behavioral of New_FSM is
 TYPE StateType IS
  (S_Initial,S_1right,S_2right,S_3right,S_1wrong,S_2wrong,S_3wrong);
 signal currentstate, nextstate: StateType;
begin
-- TODO: The next step is to define the actual transitions.
-- The Transitions are what happens on the actual clock edge.
-- Because the machine that we are building is relatively simple, the value of the Next State
-- will always go to the Current state on the rising edge of a clock.
-- i.e. Current state is assigned the value of Next state on the rising_edge of the clock input.
 process(clk)
 if(rising_edge(clk)) Then
  currentstate <= nextstate;
 end if;
end process;

process(currentstate, lock, load)
begin
 case currentstate is
   when S_Initial =>
    right='0';
    wrong = '0';
    if load = '1' then
     if input = "011" then
      nextstate <= S_1right;
     else
      nextstate <= S_1wrong;
     end if;
    end if;
   when S_1right =>
    right='0';
    wrong = '0';
    if load = '1' then
     if input = "001" then
      nextstate <= S_2right;
     else
      nextstate <= S_2wrong;
     end if;
    end if;
   when S_2right =>
    right='0';
    wrong = '0';
    if load = '1' then
     if input = "100" then
      nextstate <= S_3right;
     else
      nextstate <= S_3wrong;
     end if;
    end if;
   when S_3right =>
    right = '1';
    wrong = '0';
    if lock ='1' then
     nextstate <= S_inital;
    end if;
   when S_1wrong =>
    right = '0';
    wrong = '0';
    if load = '1' then
     nextstate <= S_2wrong;
    end if;
   when S_2wrong =>
    right = '0';
    wrong = '0';
    if load = '1' then
     nextstate <= S_3wrong;
    end if;
   when S_3wrong =>
    right = '0';
    wrong = '1';
    if load = '1' then
     if input = "011" then
      nextstate <= S_1right;
     else
      nextstate <= S_1wrong;
     end if;
    end if;
   when others => nextstate <= S_initial;
 end case;
end process;

end Behavioral;

0.5Hz Clock, Csse Homework

--- Alexander Hoffman
--- 42004259

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clkdiv is
    Port ( mclk : in  STD_LOGIC;
           clr : in  STD_LOGIC;
           clk05 : out STD_LOGIC);
end clkdiv;

architecture Behavioral of clkdiv is

signal q : STD_LOGIC_VECTOR(27 downto 0);
signal r : STD_LOGIC;

begin
process(mclk,clr)
begin
if mclk'event and mclk = '1' then
if clr ='1' then
q <= X"0000000";
r <= '0';
clk05 <= r;
elsif q < X"2faf080" then
q <= q + 1;
else
q <= X"0000000";
r <= not r;
clk05 <= r;
end if;
end if;
end process;

end Behavioral;

This needs to be shared with some nerds

This game is getting so intensely good!

Csse quiz error

R2R ladder

50hz

16k Hz

Voltage Divider

CSSE hardware quiz 1 VHDL code

#################### NOTAND.VHD###############################

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity notand is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           f : out  STD_LOGIC);
end notand;

architecture Behavioral of notand is

begin

process(a,b)
begin
f<= a nand b;
end process;

end Behavioral;

###############################################################

##########################################QUIZ.VHD############

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity quiz is

    Port ( a : in  STD_LOGIC;

           b : in  STD_LOGIC;

           f : out  STD_LOGIC);

end quiz;

architecture Behavioral of quiz is

component notand is

port( a : in std_logic;

b : in std_logic;

f : out std_logic);

end component;

signal s1,s2,s3 : std_logic;

begin

c1: notand port map (a,b,s1);

c2: notand port map (s1,a,s2);

c3: notand port map (s1,b,s3);

c4: notand port map (s2,s3,f);

end Behavioral;

###############################################################

###########################CONSTRAINTS.UCF###################

net "a" loc = "p38";

net "b" loc = "p36";

net "f" loc = "p15";

##############################################################