lab pc device manager

MULTI


----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    14:31:23 05/09/2011
-- Design Name:
-- Module Name:    fourBitMultByTwo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fourBitMultByTwo is
    Port ( input : in  STD_LOGIC_VECTOR (3 downto 0);
           load : in  STD_LOGIC;
           clr : in  STD_LOGIC;
           en : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           output : out  STD_LOGIC_VECTOR (3 downto 0));
end fourBitMultByTwo;

architecture Behavioral of fourBitMultByTwo is

type state_type is (s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15);
signal currentstate, nextstate : state_type := s0;

begin

process(clk, clr)
begin
if clr = '1' then
currentstate <= s0;
elsif rising_edge(clk) then
currentstate <= nextstate;
end if;
end process;

process(currentstate, en, load)
begin
if load = '1' then
case input is
when X"0" => nextstate <= s0;
when X"1" => nextstate <= s1;
when X"2" => nextstate <= s2;
when X"3" => nextstate <= s3;
when X"4" => nextstate <= s4;
when X"5" => nextstate <= s5;
when X"6" => nextstate <= s6;
when X"7" => nextstate <= s7;
when X"8" => nextstate <= s8;
when X"9" => nextstate <= s9;
when X"A" => nextstate <= s10;
when X"B" => nextstate <= s11;
when X"C" => nextstate <= s12;
when X"D" => nextstate <= s13;
when X"E" => nextstate <= s14;
when X"F" => nextstate <= s15;
end case;
else
case currentstate is
when s0 =>
if en = '1' then
nextstate <= s0;
else
nextstate <= s0;
end if;
when s1 =>
if en = '1' then
nextstate <= s2;
else
nextstate <= s1;
end if;
when s2 =>
if en = '1' then
nextstate <= s4;
else
nextstate <= s2;
end if;
when s3 =>
if en = '1' then
nextstate <= s6;
else
nextstate <= s3;
end if;
when s4 =>
if en = '1' then
nextstate <= s8;
else
nextstate <= s4;
end if;
when s5 =>
if en = '1' then
nextstate <= s10;
else
nextstate <= s5;
end if;
when s6 =>
if en = '1' then
nextstate <= s12;
else
nextstate <= s6;
end if;
when s7 =>
if en = '1' then
nextstate <= s14;
else
nextstate <= s7;
end if;
when s8 =>
if en = '1' then
nextstate <= s1;
else
nextstate <= s8;
end if;
when s9 =>
if en = '1' then
nextstate <= s3;
else
nextstate <= s9;
end if;
when s10 =>
if en = '1' then
nextstate <= s5;
else
nextstate <= s10;
end if;
when s11 =>
if en = '1' then
nextstate <= s7;
else
nextstate <= s11;
end if;
when s12 =>
if en = '1' then
nextstate <= s9;
else
nextstate <= s12;
end if;
when s13 =>
if en = '1' then
nextstate <= s11;
else
nextstate <= s13;
end if;
when s14 =>
if en = '1' then
nextstate <= s13;
else
nextstate <= s14;
end if;
when s15 =>
if en = '1' then
nextstate <= s15;
else
nextstate <= s15;
end if;
end case;
end if;
end process;

process(currentstate)
begin
case currentstate is
when s0 =>
output <= X"0";
when s1 =>
output <= X"1";
when s2 =>
output <= X"2";
when s3 =>
output <= X"3";
when s4 =>
output <= X"4";
when s5 =>
output <= X"5";
when s6 =>
output <= X"6";
when s7 =>
output <= X"7";
when s8 =>
output <= X"8";
when s9 =>
output <= X"9";
when s10 =>
output <= X"A";
when s11 =>
output <= X"B";
when s12 =>
output <= X"C";
when s13 =>
output <= X"D";
when s14 =>
output <= X"E";
when s15 =>
output <= X"F";
end case;
end process;

end Behavioral;


COUNT


----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    14:07:04 05/09/2011
-- Design Name:
-- Module Name:    fourBitBcdCounter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fourBitBcdCounter is
    Port ( en : in  STD_LOGIC;
           clr : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           output : out  STD_LOGIC_VECTOR (3 downto 0);
           flag : out  STD_LOGIC);
end fourBitBcdCounter;

architecture Behavioral of fourBitBcdCounter is

type state_type is (s0, s1, s2, s3, s4, s5, s6, s7, s8, s9);
signal currentstate, nextstate : state_type := s0;

begin

process(clk, clr)
begin
if clr = '1' then
currentstate <= s0;
elsif rising_edge(clk) then
currentstate <= nextstate;
end if;
end process;

process(currentstate, en)
begin
case currentstate is
when s0 =>
if en = '1' then
nextstate <= s1;
else
nextstate <= s0;
end if;
when s1 =>
if en = '1' then
nextstate <= s2;
else
nextstate <= s1;
end if;
when s2 =>
if en = '1' then
nextstate <= s3;
else
nextstate <= s2;
end if;
when s3 =>
if en = '1' then
nextstate <= s4;
else
nextstate <= s3;
end if;
when s4 =>
if en = '1' then
nextstate <= s5;
else
nextstate <= s4;
end if;
when s5 =>
if en = '1' then
nextstate <= s6;
else
nextstate <= s5;
end if;
when s6 =>
if en = '1' then
nextstate <= s7;
else
nextstate <= s6;
end if;
when s7 =>
if en = '1' then
nextstate <= s8;
else
nextstate <= s7;
end if;
when s8 =>
if en = '1' then
nextstate <= s9;
else
nextstate <= s8;
end if;
when s9 =>
if en = '1' then
nextstate <= s0;
else
nextstate <= s9;
end if;
end case;
end process;

process(currentstate)
begin
case currentstate is
when s0 =>
output <= X"0";
flag <= '0';
when s1 =>
output <= X"1";
flag <= '0';
when s2 =>
output <= X"2";
flag <= '0';
when s3 =>
output <= X"3";
flag <= '0';
when s4 =>
output <= X"4";
flag <= '0';
when s5 =>
output <= X"5";
flag <= '0';
when s6 =>
output <= X"6";
flag <= '0';
when s7 =>
output <= X"7";
flag <= '0';
when s8 =>
output <= X"8";
flag <= '0';
when s9 =>
output <= X"9";
flag <= '1';
end case;
end process;
end Behavioral;

s(^_-)-d

http://www.farnell.com/datasheets/93496.pdf

http://au.element14.com/stmicroelectronics/ld1117av33/ic-v-reg-ldo-3-3v-1117-to-220-3/dp/1087165

max 756 0.7V-5V to 5V circuit

http://www.eleccircuit.com/max756-25v-35v-to-5v-step-up-dc-dc-converter/

Mapped circuit up without the second 1uF cap that decouples the output and worked perfectly

I R REGULATORZ

http://www.farnell.com/datasheets/16088.pdf

Final power shizzle

MAX756

http://au.element14.com/maxim-integrated-products/max756cpa/step-up-reg-3v-5v-out-dip8-756/dp/1290853
http://www.farnell.com/datasheets/60116.pdf

Schottky Diode

http://au.element14.com/hy-electronics/1n5817/schottky-diode-1a-20v-do-41/dp/1843507

Capacitors

150uF
100uF
0.1uF

Inductors

22uH